A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET

Abraham Gonzalez
Jerry ZhaoBen KorpanHasan GencColin SchmidtJohn Charles WrightAyan BiswasAlon AmidFarhana SheikhAnton SorokinSirisha KaleMani YalamanchiRamya YarlagaddaMark FlanniganLarry AbramowitzElad AlonYakun Sophia ShaoKrste AsanovicBorivoje Nikolic

This work presents a 16mm 2 heterogeneous RISC-V system-on-a-chip (SoC) composed of a high-performance out-of-order core, energy-efficient in-order core, data-parallel vector accelerator, and systolic array deep neural network (DNN) accelerator in low-power Intel 22FFL for general-purpose compute, DNN, and vector workloads. The heterogeneous RISC-V SoC is composed of fully open-source components, including a second-generation Berkeley Out-of-Order Machine (BOOM) with a non-speculative mode attached to a Hwacha vector accelerator, a Rocket in-order core attached to a Gemmini systolic array DNN accelerator, as well as a IMiB L2 cache and off-chip I/Os. Combined, the variety of heterogeneous compute allows for wide programmability while providing up to a 286x MOPS/W improvement or 282x MOPS improvement over the RISC-V in-order core.

URL: https://ieeexplore.ieee.org/document/9567768/authors