List of Presentations

Here, you can find project presentations in SLICE lab and contacts with the leads

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Project Name	Speaker(s)	Description	Link
Chipyard + FireSim Misc Projects	Abraham Gonzalez, abe.gonzalez@berkeley.edu	Chipyard is a one-stop shop for generating complex RISC-V hardware, including big processors, fast accelerators, and much more. Combined with FireSim, user can simulation thousands of processors accurately leveraging FPGAs in the cloud. Both Chipyard and FireSim are used across companies, academia (including here in Berkeley architecture classes), and around the world! If you are interested in building the next generation of RISC-V computer chips, feel free to reach out.	Slides
Hammer Physical Design - Misc Projects	Harrison Liew, harrisonliew@berkeley.edu	Hammer is a generator of physical design (VLSI) flows needed to implement chips. It is written in Python and has a strong emphasis on modularity, where flows can be constructed with interchangeable CAD tools and process technologies using a standardized yet generic configuration schema. It encourages flow reuse between different chips and enables advanced yet agile architecture design space exploration. Hammer is in constant development and is always in need of more features - we hope you'd like to help us out!	Slides
Fuzzing hardware models as a proxy for fuzzing hardware	Vighnesh Iyer, vighnesh.iyer@berkeley.edu	Automatic hardware coverage closure via random fuzzing is still an active research area. Previous attempts have suffered from loop latency bottlenecks where the fuzzer feedback takes too long to generate to iterate the genetic algorithm sufficiently fast. We will work on fuzzing hardware models (e.g. spike, gem5) using AFL and experimentally checking whether increased model coverage corresponds to better RTL coverage and enables the fuzzer to generate better stimulus, faster.	Slides
RISC-V IoT Processor PPA Analysis	Dan Fritchman, dan_fritchman@berkeley.edu & Vighnesh Iyer, vighnesh.iyer@berkeley.edu	We aim to compare the performance, power, and area (PPA) of several popular IoT open-source RISC-V processors, using the open SkyWater 130 technology and open-source RTL-to-GDS OpenROAD CAD flow. We will systematically evaluate the processors, investigating their parameterization space and the microarchitectural tradeoffs each of them make.	Slides
Architecture specific algorithms (and systems to implement them)	Grace Dinh,gnd@berkeley.edu	Given some algorithms, find algorithms and lower bounds on running those algorithms on modern architectures, and develop programming systems (compilers, etc.) to make doing that easy, (current projects: EXOlang, a language that separates the “what do we want to compute?” from “how do we compute it?” and MoST, a schedule description system on top of it). Projects available for both students interested in theory and programming systems.	Slides
Metalift: building compilers using program synthesis	Sahil Bhatia, sahilbhatia@berkeley.edu	MetaLift is a compiler generator. Unlike traditional syntax-driven compilers, which consists of rules that recognize patterns in the input code and translate them into the target language, MetaLift uses verified lifting to search for possible candidate programs in the target language that the given input can be translated to. This frees you from the need to devise, check, and maintain those pesky syntax-driven rules!	Slides
RayLEAF- Distributed ML, Federated Learning	Ayush Sehgal,ayushs25@berkeley.edu & Richard Hu, r.hu@berkeley.edu	RayLEAF is a benchmark for federated learning implemented using Ray. Currently, we are working on examining the effects of compressing client model updates on the server's accuracy and performance and in the future, we look to implement newer algorithms for federated learning. If you're interested in distributed machine learning and privacy, please reach out!	Slides