misc:acronyms
Table of Contents
Acronyms and Terms
SLICE Terms
- SLICE:
- ADEPT: Agile Design of Efficient Processing Technologies
- BAG: Berkeley Analog Generator: A Chisel like technology for generating analog circuits.
- BOOM: Berkeley Out-of-Order Machine
- BROOM: Berkeley Resilient Out-of-Order Machine
- Chisel Range-analysis: Instead of declaring a width for a wire instead specify minimum and maximum values.
- Chisel: Constructing Hardware in a Scala Embedded Language, a generator approach to circuit design.
- Concolic: A form of testing that combines the use of Concrete and Symbolic values
- Differentiable Halide:
- Diplomacy: Parameter-negotiation library found in rocket-chip
- DSSoC: Domain-specific System on Chip
- EAGLE:
- F1: AWS Instance Type with an attached FPGA
- FCL: Firrtl Command Language, a scripting language for firrtl transforms, derived from the Scala REPL (read-eval-print-loop)
- Firebox: Novel Computer Architecture for Datacenters
- FireSim: Firebox Simulator
- FIRRTL: Flexible Intermediate Representation for RTL
- Generator: A program that generates hardware descriptions
- Hammer: Physical design generator.
- HCL: Hardware Construction Language. Generate hardware using better parameterizable hardware abstractions
- HLS: High Level Synthesis, attempts to create hardware from analysis of an generic algorithmic description. In contrast to HCL
- Hwacha: Generator for RISC-V vector architecture
- LAMP: Linux-Apache-MySQL-PHP a software stack that is you need for a complete website. The pieces are now quite fungible.
- Rocket-Chip: Generator for RISC-V scalar architecture
- Shenzhen:
- VERGE:
General Terms
- AES: Advanced Encryption Standard
- ALU: Arithmetic Logic Unit
- AMR: Adaptive Mesh Refinement
- ATLAS: Automatically Tuned Linear Algebra Software
- AVX: Advanced Vector Extensions (Intel)
- BCOO: Blocked Coordinate (sparse matrix format)
- BCSR: Blocked Compressed Sparse Row (sparse matrix format)
- BIOS: Basic Input/Output System
- BLAS: Basic Linear Algebra Subroutines
- CFD: Computational Fluid Dynamics
- CG: Conjugate Gradient
- CMOS: Complementary Metal-Oxide-Semiconductor
- CMT: Chip Multithreading (Multicore + Multithreading)
- COO: Coordinate (sparse matrix format)
- CPU: Central Processing Unit
- CRC: Cyclic Redundancy Check
- CSC: Compressed Sparse Column (sparse matrix format)
- CSR: Compressed Sparse Row (sparse matrix format)
- CUDA: Compute Unified Device Architecture (NVIDIA)
- DAG: Directed Acyclic Graph
- DDR: Double Data Rate (DRAM)
- DGEMM: Double-Precision General Matrix-Matrix Multiplication
- DIB: Dual Independent (front side) Bus
- DIMM: Dual In-line Memory Module (DRAM)
- DIVPD: Divide, Parallel, Double-Precision (an SSE instruction)
- DLP: Data-Level Parallelism
- DMA: Direct Memory Access
- DRAM: Dynamic Random Access Memory
- ECC: Error-Correcting Codes
- EIB: Element Interconnect Bus (Cell)
- ELL: Sparse matrix format used by ELLPACK
- FBDIMM: Fully Buffered DIMM
- FFT: Fast Fourier Transform
- FFTW: Fastest Fourier Transform in the West
- FMA: Fused Multiply-Add
- FMM: Fast Multipole Method
- FPU: Floating-Point Unit
- FSB: Front Side Bus
- GCSR: General Compressed Sparse Row
- GPU: Graphics Processing Unit
- GTC: Gyrokinetic Toroidal Code
- HPC: High Performance Computing
- ILP: Instruction-Level Parallelism
- IRAM: Intelligent RAM (a chip from Berkeley)
- ISA: Instruction Set Architecture
- KCCA: Kernel Canonical Correlation Analysis
- LBM: Lattice-Boltzmann Method
- LBMHD: Lattice-Boltzmann Magnetohydrodynamics
- LU: LU Factorization (Lower-Upper Triangular)
- MACC: Multiply Accumulate
- MCH: Memory Controller Hub
- MCM: Multi-Chip Module
- MESI: Cache Coherency Protocol
- MFC: Memory Flow Controller (Cell)
- MHD: Magnetohydrodynamics
- MLP: Memory-Level Parallelism
- MOESI: Cache Coherency Protocol
- MPI: Message Passing Interface
- MPICH: A Free, Portable Implementation of MPI
- MT: Multithreading
- NNZ: Number of Non-Zeros in a Sparse Matrix
- NUMA: Non-Uniform Memory Access
- OSKI: Optimized Sparse Kernel Interface
- PhiPAC: Portable High Performance Ansi C
- PDE: Partial Differential Equation
- PIC: Particle in Cell code
- PPE: PowerPC Processing Element (Cell)
- QCD: Quantum Chromodynamics
- RGB: Red, Green, Blue
- RISC: Reduced Instruction Set Computing
- RTL: Register Transfer Language
- SIMD: Single-Instruction, Multiple-Data
- SIP: System In Package approach to integration
- SKY: Skyline Sparse Matrix Format
- SMP: Shared Memory Parallel (A multiprocessor computer)
- SOR: Successive Over-Relaxation
- SPD: Symmetric, Positive Definite
- SPE: Synergistic Processing Element (Cell)
- SPMD: Single-Program, Multiple-Data
- SpMV: Sparse Matrix-Vector Multiplication
- SpTS: Sparse Triangular Solve
- SPU: Synergistic Processing Unit (Cell)
- SSE: Streaming SIMD Extensions (Intel)
- STI: Sony-Toshiba-IBM — the partnership that produced Cell
- TLB: Translation Lookaside Buffer
- TLP: Thread-Level Parallelism
- UMA: Uniform Memory Access
- UPC: Unified Parallel C
- VF: Victoria Falls (multisocket Niagara2 SMP)
- VIS: Visual Instruction Set (Sun's SIMD)
- VL: Vector Length
- VLIW: Very Long Instruction Word
- VLSI: Very Large Scale Integration
- VMX: PowerPC SIMD unit (AltiVec)
- WB: Write-Back cache
- WT: Write-Through cache
- XDR: RAMBUS eXtreme Data Rate DRAM
misc/acronyms.txt · Last modified: 2021/12/07 12:34 by kilov