ug_mplace:main
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ug_mplace:main [2022/02/18 13:29] – riamelendres | ug_mplace:main [2022/02/23 11:35] – riamelendres | ||
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^Project Name ^Speaker(s) ^Description ^Link ^ | ^Project Name ^Speaker(s) ^Description ^Link ^ | ||
- | | Chipyard + FireSim Misc Projects | Abraham Gonzalez, abe.gonzalez@berkeley.edu | Chipyard is a one-stop shop for generating complex RISC-V hardware, including big processors, fast accelerators, | + | | Chipyard + FireSim Misc Projects | Abraham Gonzalez, abe.gonzalez@berkeley.edu | Chipyard is a one-stop shop for generating complex RISC-V hardware, including big processors, fast accelerators, |
- | |Hammer Physical Design - Misc Projects | Harrison Liew, harrisonliew@berkeley.edu | Hammer is a generator of physical design (VLSI) flows needed to implement chips. It is written in Python and has a strong emphasis on modularity, where flows can be constructed with interchangeable CAD tools and process technologies using a standardized yet generic configuration schema. It encourages flow reuse between different chips and enables advanced yet agile architecture design space exploration. Hammer is in constant development and is always in need of more features - we hope you'd like to help us out! | https:// | + | |Hammer Physical Design - Misc Projects | Harrison Liew, harrisonliew@berkeley.edu | Hammer is a generator of physical design (VLSI) flows needed to implement chips. It is written in Python and has a strong emphasis on modularity, where flows can be constructed with interchangeable CAD tools and process technologies using a standardized yet generic configuration schema. It encourages flow reuse between different chips and enables advanced yet agile architecture design space exploration. Hammer is in constant development and is always in need of more features - we hope you'd like to help us out! | [[https:// |
+ | | Fuzzing hardware models as a proxy for fuzzing hardware |Vighnesh Iyer, vighnesh.iyer@berkeley.edu | ||
+ | | RISC-V IoT Processor PPA Analysis | Dan Fritchman, dan_fritchman@berkeley.edu & Vighnesh Iyer, vighnesh.iyer@berkeley.edu | We aim to compare the performance, | ||
+ | | Architecture specific algorithms (and systems to implement them) | Grace Dinh, | ||
+ | | Metalift: building compilers using program synthesis | Sahil Bhatia, sahilbhatia@berkeley.edu | MetaLift is a compiler generator. Unlike traditional syntax-driven compilers, which consists of rules that recognize patterns in the input code and translate them into the target language, MetaLift uses verified lifting to search for possible candidate programs in the target language that the given input can be translated to. This frees you from the need to devise, check, and maintain those pesky syntax-driven rules! | [[https:// | ||
+ | | RayLEAF- Distributed ML, Federated Learning | Ayush Sehgal, |
ug_mplace/main.txt · Last modified: 2022/02/23 15:57 by riamelendres