NeCTAr and RASoC: Tale of Two Class SoCs for Language Model Interference and Robotics in Intel 16
Viansa Schmulbach; Jason Kim; Ethan Gao; Nikhil Jha; Ethan Wu; Oliver Yu
- Two 16nm heterogeneous system-on-chip designs developed from concept to chip tapeout in <15 weeks by a team of mostly undergraduate students with no prior chip design experience
- Both chips contain: 64b-wide TileLink unidirectional torus NoC, on-chip 64KB scratchpad, 256KB of L2$ in four banks, and an on-chip 10MHz.2.5GHz Intel-provided PLL
- On-chip peripherals include: 52x GPIO, 3x UART, 2x XIP QSPI Flash/PSRAM, 6x PWM, 2x I2C, 1x 4ch. QSPI, and Serial Tilelink